 Kaixin YangPh.D. Student in DesCyPhy Lab at USC | I am Kaixin Yang (杨凯欣), a Ph.D. student in DesCyPhy Lab at University of Southern California (USC), advised by Prof. Pierluigi Nuzzo. I am interested in hardware security and trustworthy hardware design, as well as machine learning (ML)-based approaches to them. Recently, I focus on logic locking for gate-level VLSI design, Satisfiability (SAT) based attacks and ML-based attacks on encrypted design, secure high level synthesis, metrics for evaluating and guiding trustworthy design, and design space exploration for risk-free hardware design. |
EDUCATION
| 2025 | Ph.D. student, Computer Engineering, USC |
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| 2021 | Master's Degree, Electrical Engineering, USC |
| 2019 | Bachelor's Degree, Electronic and Information Science and Technology, Peking University |
EXPERIENCE
| May 2024 - Present | CAD Intern, Intel |
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| Aug 2020 - Present | Research Assistant, USC |
| Spring 2022 | Teaching Assistant, EE577a, USC |
| Spring 2019 | Teaching Assistant, Practice for Programming, PKU |
| Fall 2021 | Teaching Assistant, EE477L, USC |
| Summer 2023 | VSI Program Mentor, USC |
| Summer 2023, Summer 2022 | SHINE Program Mentor, USC |
| Spring 2024, Fall 2022, Fall 2021 | EE581 Project Mentor, USC |
HONORS AND AWARDS
| 2022 | DAC Young Fellow |
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| 2019 | Annenberg Fellowship |
NEWS
- May 2024: I will join Intel as a CAD intern.
- Apr 2024: Our paper "DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks has been accepted at International Symposium on Quality Electronic Design(ISQED) 2024.
- Apr 2023: Our paper "Similarity-Based Logic Locking Against Machine Learning Attacks" has been accepted at Design Automation Conference (DAC) 2023.
- Apr 2023: Our collaboration work "Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP" with Prof. Beerel's group has been accepted at International Symposium on Quality Electronic Design(ISQED) 2023.
- Mar 2023: Our paper "On the Security of Sequential Logic Locking Against Oracle-Guided Attacks" has been published at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
- Feb 2023: Our paper introducing a new logic locking technique leveraging similarity between gates or wires to mitigate machine learning-based attacks has been accepted at Design Automation Conference (DAC) 2023.
- Apr 2022: I have been selected to participate in the Young Fellows program promoted by the 59h Design Automation Conference (DAC).
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