I am Kaixin Yang (杨凯欣), a Ph.D. student in DesCyPhy Lab at University of Southern California (USC), advised by Prof. Pierluigi Nuzzo. I am interested in hardware security and trustworthy hardware design, as well as machine learning (ML)-based approaches to them. Recently, I focus on logic locking for gate-level VLSI design, Satisfiability (SAT) based attacks and ML-based attacks on encrypted design, secure high level synthesis, metrics for evaluating and guiding trustworthy design, and design space exploration for risk-free hardware design.
Aug 2020 - Present | Research Assistant, USC
Jan-May 2022 | Teaching Assistant, EE577a, USC
Aug-Dec 2021 | Teaching Assistant, EE477L, USC
Jul-Aug 2023| VSI Program Mentor, USC
Jun-Jul 2023, Jun-Jul 2022 | SHINE Program Mentor, USC
Aug-Dec 2022, Aug-Dec 2021 | EE581 Project Mentor, USC
2024 | Ph.D. student, Computer Engineering, USC
2021 | Master's Degree, Electrical Engineering, USC
2019 | Bachelor's Degree, Electronic and Information Science and Technology, Peking University
2022 | DAC Young Fellow
2019 | Annenberg Fellowship
[Apr 2023][Paper] Our paper "Similarity-Based Logic Locking Against Machine Learning Attacks" has been accepted at Design Automation Conference (DAC) 2023.
[Apr 2023][Paper] Our collaboration work "Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP" with Prof. Beerel's group has been accepted at International Symposium on Quality Electronic Design(ISQED) 2023.
[Mar 2023][Paper] Our paper "On the Security of Sequential Logic Locking Against Oracle-Guided Attacks" has been published at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
[Feb 2023][Paper] Our paper introducing a new logic locking technique leveraging similarity between gates or wires to mitigate machine learning-based attacks has been accepted at Design Automation Conference (DAC) 2023.
[Apr 2022][Award] I have been selected to participate in the Young Fellows program promoted by the 59h Design Automation Conference (DAC).