We have two subgroups, focusing on cyber-physical system design and trustworthy SoC design respectively.
Advisor: Prof. Pierluigi Nuzzo
Postdoc: Michele Lora, Luca Geretti, Dengwang Tang
Ph.D. students: Chanwook Oh, Subhajit Dutta Chowdhury, Nikhil Vijay Naik, Krishna Chaitanya Kalagaria, Yifeng Xiao, Kevin (Chia-Ming) Chang, Matthew Low, Zhiyu Ni, and me
Alumni: Dhruva Kartik (Postdoc, Amazon), Yinghua Hu (PhD, Synopsys)
Y. Hu, K. Yang, S. Nazarian, P. Nuzzo, "SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption," in VLSI-SoC: Design Trends, Springer, pp. 255-278, Jul. 2021.
Y. Hu, Y. Zhang, K. Yang, D. Chen, P. A. Beerel, P. Nuzzo, "On the Security of Sequential Logic Locking Against Oracle-Guided Attacks," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Mar. 2023.
S. D. Chowdhury, K. Yang, P. Nuzzo, "Similarity-Based Logic Locking Against Machine Learning Attacks," Design Automation Conference (DAC), 2023.
D. Chen, X. Zhou, Y. Hu, Y. Zhang, K. Yang, P. A. Beerel, P. Nuzzo, "Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP," International Symposium on Quality Electronic Design (ISQED), Apr. 2023.
Y. Hu, Y. Zhang, K. Yang, D. Chen, P. A. Beerel, P. Nuzzo, "Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption," Proc. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 281-291, Dec. 2021.
S. Dutta Chowdhury, K. Yang, P. Nuzzo, "ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineering," Proc. Int. Conf. Computer Aided Design (ICCAD), pp. 1-9, Nov. 2021.
Y. Hu, K. Yang, S. D. Chowdhury and P. Nuzzo, "Risk-Aware Cost-Effective Design Methodology for Integrated Circuit Locking," Proc. IEEE/ACM Design Automation and Testing in Europe Conf. (DATE), pp. 1182-1185, Feb. 2021.
Y. Hu, K. Yang, S. Nazarian and P. Nuzzo, "SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption Scheme," Proc. IFIP/IEEE Int. Conf. Very Large-Scale Integration (VLSI-SoC), pp. 129-134, Oct. 2020.